1. Field of the Invention
The present invention relates to a method of forming a via hole, and more particularly, to a method of forming a via hole by using a blocking layer.
2. Description of the Prior Art
Lithography processing, which is an essential technology when manufacturing integrated circuits, is used for defining geometries, features, lines, or shapes onto a die or wafer. In the integrated circuit making processes, lithography plays an important role in limiting feature size. By using lithography, a circuit pattern can be precisely and accurately transferred onto a die or wafer. However, with the increasing complexity and integration of the integrated circuits, conventional lithography process has met a lot of difficulties.
For example, in the process of manufacturing via holes, the pore size of the via hole and the distance between each via hole will be limited by the resolution of the photo mask. In prior art methods for producing via holes, the photo resist layer serves as an etching mask for etching the underlying dielectric layer. For the 22 nm process, the pitch (the distance of centers of two neighboring via holes) for via holes must be lower than 90 nm and the “after development inspect critical dimension” (ADICD) must be around 35-50 nm. For the current lithographic tools, it is impossible to create contact holes with pitch lower than 90 nm in one exposure. The current solution is that the desired via holes are patterned by two exposures with two photo masks on a photo resist layer, and then followed by one etching step. Thus, a via hole array with less pitch can be obtained.
By the aforementioned two exposing processes, a regular arrangement of the via hole array can be obtained. However, the method is suitable for forming the memory array, but may not be suitable for forming an integrated circuit layout which has irregular via hole arrangement.